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How to read device data and file registers in Q series
Specify the target memory in the Read from PLC window and execute reading. More Details >>
- No:22564
- Release Date:2018/09/03 17:29
- Category: MELSEC-Q Series
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Specification method of high-speed timer
To use a high-speed timer, insert a circuit of application instruction such as "OUTH T0 K100". More Details >>
- No:22549
- Release Date:2018/09/03 17:28
- Category: MELSEC-Q Series
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It is an embedded RTOS (real-time OS) developed by Wind River, which is proven worldwide as reliable and stable.The version of the operation system installed... More Details >>
- No:22544
- Release Date:2018/09/03 17:28
- Category: MELSEC-Q Series
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MX Component Version 3's compatibility with Visual Studio 2010
MX Component Version 3.15R or later supports Visual Basic and Visual C++ of Visual Studio 2010. More Details >>
- No:22543
- Release Date:2018/09/03 17:28
- Category: MELSEC-Q Series
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Difference between C Controller module and programmable controller CPU module
- C Controller module: Programs are created using C and C++ languages. The programs run based on each task and parallel processing of multiple tasks base... More Details >>
- No:22542
- Release Date:2018/09/03 17:28
- Update:2018/09/20 15:05
- Category: MELSEC-Q Series
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Maximum apparent power of the power supplies of Q00JCPU and Q00UJCPU
Both are 105 VA. More Details >>
- No:22538
- Release Date:2018/09/03 17:28
- Category: MELSEC-Q Series
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CPU modules supporting the serial communication function
CPU modules supporting the serial communication function are as follows. - Q00UJCPU,Q00UCPU,Q01UCPU - Q02UCPU 10102 or later (with GX Works2 1.15R or l... More Details >>
- No:22530
- Release Date:2018/09/03 17:28
- Update:2018/09/20 14:37
- Category: MELSEC-Q Series
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MX Component Version 3's compatibility with 64-bit Windows 7
MX Component Version 3.15R or later supports 64-bit Windows 7. More Details >>
- No:22520
- Release Date:2018/09/03 17:28
- Category: MELSEC-Q Series
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Regarding TPDO and RPDO allocation
RWr is allocated to TPDO and RWw is allocated to RPDO. More Details >>
- No:44479
- Release Date:2024/07/02 19:06
- Category: MELSEC iQ-F Series , Network/Communication
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Regarding the FX5S CPU Module Line-up
The line-up of input and output points of the FX5S CPU module is as follows. ・30 points (Input: 16 points, Output: 14 points) ・40 points (Input: 24 points,... More Details >>
- No:39340
- Release Date:2023/02/14 17:28
- Category: MELSEC iQ-F Series , CPU Module
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